This application claims priority from Korean Patent Application No. 2002-87241 filed on Dec. 30, 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a capacitor of a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
As the integration density of semiconductor memory devices increases, the space taken up by a memory cell area typically decreases. A decrease in cell capacitance is typically a serious obstacle in increasing the integration of dynamic random access memory (DRAM) devices having storage capacitors.
In a high voltage (10V or higher) device such as Liquid Crystal Device (LCD) Drive Integrated Circuit (IC) or LDI, a decrease in the cell capacitance raises the boosting frequency to increase power dissipation, thereby making it difficult to scale down the entire chip size. For memory devices, a decrease in the cell capacitance not only lowers the ability to read a memory cell and increases a soft error rate, but it also hinders the operation of the device at low voltages and causes excessive power consumption during the operation of the device. Therefore, a method for increasing cell capacitance needs to be developed for the manufacture of a highly integrated semiconductor memory device.
Generally, dielectric properties of the cell capacitance can be evaluated by the equivalent oxide thickness (Toxeq) and the leakage current density. The Toxeq is a value obtained by converting the thickness of a dielectric layer formed of a material other than a silicon oxide substance into the thickness of a dielectric layer formed of a silicon oxide substance. As the value of the Toxeq becomes smaller, the capacitance increases. Also, it is preferable that the leakage current density has a small value in order to improve the electrical properties of a capacitor.
In a conventional method, to increase the cell capacitance, a dielectric layer is formed of a combination of a silicon oxide layer (SiO2, hereinafter represented as ‘O’) and a silicon nitride layer (Si3N4, hereinafter represented as ‘N’), for example, an NO, ON, or ONO layer. However, because the silicon oxide and silicon nitride layers have low dielectric constants, this method is limited in improving the cell capacitance.
Thus, research is being done on methods in which a silicon nitride layer or a silicon oxide layer is replaced by a high dielectric layer having a high dielectric constant for the dielectric layer of a capacitor. Accordingly, various metal oxides having high dielectric constants are potentially strong candidates for this new capacitor dielectric layer material.